1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device using a signal boosted to a predetermined voltage level.
2. Description of the Background Art
Some semiconductor devices use a signal boosted to a predetermined voltage level rather than a signal of an ordinary power supply voltage level, in order to obtain stability of operation of an internal circuit or the like. Some DRAMs (Dynamic Random Access Memories) have a shared sense amplifier configuration in which a sense amplifier is shared by two separate memory blocks. In the DRAM having the shared sense amplifier configuration, the above-described boosted signal is used as a control signal controlling selective connection of the sense amplifier to one of the two memory blocks.
The DRAM will be described with reference to the drawings as a conventional semiconductor device. FIG. 9 is a block diagram showing a configuration of a conventional DRAM.
In FIG. 9, a DRAM 200 includes memory cell arrays 1a to 1d, sense amplifier units 2a, 2b, a row decoder 3, a word driver 4, a row address buffer 5, an RAS buffer 6, a .phi.x generating circuit 7, a .phi.x subdecoder 12, a row predecoder 15, a column address buffer 16, a column predecoder 17, a column decoder 18, an I/O decoder 19, an R/W control unit 20, a CAS buffer 21, an R/W buffer 22, an input buffer 23, an output buffer 24, and a sense amplifier control circuit 25.
DRAM 200 includes terminals P1 to P6 for input/output a signal from/to outside. To terminal P1, input is a row address strobe signal /RAS ("/" indicates an inverted signal) which provides a timing at which row addresses provided in a time sharing manner are incorporated into the device. To terminal P2, input are row addresses RA0 to RA8 and column addresses CA0 to CA8 provided in a timing sharing manner. To terminal P3, input is a column address strobe signal /CAS which provides a timing at which the column addresses are incorporated into the device. To terminal P4, input is a read/write control signal R/W defining the read/write operation. To terminal P5, input is input data D.sub.IN. Output data D.sub.OUT is output from terminal P6. DRAM 200 further includes a terminal supplying power supply voltage V.sub.CC serving as a reference voltage and a terminal supplying ground potential GND (not shown).
Row address buffer 5 receives 9-bit address signals A0 to A8 provided to terminal P2, and generates complementary internal row address signals RA0, /RA0, . . . , RA8, /RA8 in response to an internal control signal from RAS buffer 6.
Row predecoder 15 decodes internal row address signals RA2, /RA2, . . . , RA7, /RA7 from row address buffer 5, and generates 12 predecode signals in total of X1 to X4 (generally referred to as "Xi"), X5 to X8 (generally referred to as "Xj"), and X9 to X12 (generally referred to as "Xk").
.phi.x generating circuit 7 generates a word line drive master signal .phi.x for driving a word line in response to an internal control signal from RAS buffer 6 to output the same to .phi.x subdecoder 12.
.phi.x subdecoder 12 generates word line subdecode signals .phi.x1 to .phi.x4 in response to internal row address signals RA0, /RA0, RA1 and /RA1 from row address buffer 5, and word line drive master signal .phi.x, to output the same to word driver 4.
Row decoder 3 further decodes predecode signals Xi, Xj and Xk output from row predecoder 15, and generates a decode signal selecting four word lines.
Word driver 4 outputs a word line drive signal WL onto one word line in response to the decode signal from row decoder 3 and word line subdecode signals .phi.x1 to .phi.x4 from .phi.x subdecoder 12.
Column address buffer 16 incorporates the address input to terminal P2 in response to the column address strobe signal /CAS from CAS buffer 21, and outputs an internal column address signal to column predecoder 17.
Column predecoder 17 outputs complementary internal column address signals to column decoder 18 in response to the internal column address signal.
Column decoder 18 outputs a column select signal CS selecting four columns in response to a column predecode signal.
Sense amplifier control circuit 25 includes an SF signal generating circuit 9, a first sense amplifier activating circuit 10, and a second sense amplifier activating circuit 11.
SF signal generating circuit 9 provides a signal activating a sense amplifier of either sense amplifier unit 2a or 2b to sense amplifier units 2a, 2b in response to the word line drive master signal .phi.x from .phi.x generating circuit 7 and the predecode signal Xi from row predecoder 15.
First sense amplifier activating circuit 10 provides a first sense amplifier activation signal to sense amplifier units 2a, 2b in response to a control signal from SF signal generating circuit 9.
Second sense amplifier activating circuit 11 provides a second sense amplifier activation signal to sense amplifier units 2a, 2b in response to the activation signal from first sense amplifier activating circuit 10.
A block select signal generating circuit 26 provides block select signals BS0 to BS3 to a shared sense control unit 27 in response to the internal row address signals RA0, RA1 from row address buffer 5 and the row address strobe signal /RAS input through RAS buffer 6.
Shared sense control unit 27 provides shared sense control signals BLIS0 to BLIS3, BLIK0 to BLIK3 to a BLI driver unit 28 in response to the block select signals BS0 to BS3 from block select signal generating circuit 26.
BLI driver unit 28 provides to sense amplifier units 2a, 2b shared sense amplifier control signals BLI0, BLI1, BLI2, BLI3 controlling a connection of a sense amplifier (not shown) included in sense amplifier units 2a, 2b and bit lines BL, /BL of memory cell arrays 1a to 1d in response to the control signals BLIS0 to BLIS3, BLIK0 to BLIK3 from shared sense control unit 27.
I/O decoder 19 decodes an internal row address signal from row address buffer 16 and an internal column address signal from column address buffer 5, and selects a pair of signal lines out of an I/O bus.
R/W buffer 22 generates a timing signal defining write/read of data in response to the read/write control signal R/W provided through terminal P4 and the column address strobe signal /CAS from CAS buffer 21, and outputs the signal to R/W control unit 20.
R/W control unit 20 connects a pair of signal lines selected by I/O decoder 19 to input buffer 23 or output buffer 24 in response to a control signal from R/W buffer 22.
Input buffer 23 receives input data D.sub.IN applied through terminal P5, and generates corresponding internal data.
Output buffer 24 receives the internal data output from R/W control unit 20 and converts the same into corresponding output data D.sub.OUT and outputs the converted data to terminal P6.
Because of the above-described configuration, corresponding to the row address and the column address applied to terminal P2, it is possible to write input data D.sub.IN applied from terminal P5 to a predetermined memory cell in memory cell arrays 1a to 1d and to read out the written data to output the same as output data D.sub.OUT from terminal P6.
Description will now be given in detail of BLI driver unit 28 with reference to the drawings. FIG. 10 is a block diagram showing a configuration of BLI driver unit 28 and sense amplifier units 2a, 2b.
In FIG. 10, BLI driver unit 28 includes BLI drivers 281 to 284. BLI driver 281 provides the shared sense amplifier control signal BLI0 to sense amplifier unit 2a in response to control signals BLIS0, BLIK0 from block select signal generating circuit 26. BLI drivers 282 to 284 operate similarly. BLI driver unit 28 includes a boosted voltage generating unit (not shown) which boosts the power supply voltage V.sub.CC to a predetermined boosted voltage V.sub.PP by using the charge pump operation of a capacitor to supply the voltage to BLI drivers 281 to 284.
Sense amplifier unit 2a includes a sense amplifier 21 and transistors Q21 to Q24. Transistors Q21 to Q24 are n-channel transistors. The gates of transistors Q21, Q22 are connected to BLI driver 281, and supplied with the shared sense amplifier control signal BLI0. The gates of transistors Q23, Q24 are connected to BLI driver 282, and supplied with the shared sense amplifier control signal BLI1. Bit line BL0 and bit line /BL0 of memory cell array 1a are respectively connected to terminals P21 and P22. Bit line BL1 and bit line /BL1 of memory cell array 1b are respectively connected to terminals P23 and P24. Since the configuration of sense amplifier unit 2b is the same as that of sense amplifier unit 2a, the description will not be repeated.
Description will first be given of operation at the time of stand-by. At stand-by, the control signals BLIS0 to BLIS3 are all at the power supply voltage V.sub.CC ("H") level, and the control signals BLIK0 to BLIK3 are all at the ground potential GND ("L") level. At this time, BLI drivers 281 to 284 are provided at the boosted voltage V.sub.PP level ("H") boosted from the power supply voltage V.sub.CC as the shared sense amplifier control signals BLI0, BLI1, BLI2, BLI3.
Description will now be given of operation in an active period. When terminals P21, P22 are selected, for example, the control signal BLIS0 attains an "H" level, and the control signal BLIK0 attains an "L" level. The control signals BLIS1 to BLIS3 attain an "L" level, and the control signals BLIK1 to BLIK3 attain an "H" level. In this case, the shared sense amplifier control signal BLI0 is provided at the boosted voltage V.sub.PP level (selected state), and the other shared sense amplifier control signals all attain an "L" level (non-selected state). When the shared sense amplifier control signal BLI0 attains an "H" level, transistors Q21, Q22 are turned on, and connects sense amplifier 21 and the side of terminals P21, P22. On the other hand, since the shared sense amplifier control signals BLI1 to BLI3 at an "L" level (the ground potential GND) are input to transistors Q23 to Q28, transistors Q23 to Q28 are all turned off, and disconnects sense amplifiers 21, 22 and each terminal side.
As a selected state of the shared sense amplifier control signal, the value of the boosted voltage V.sub.PP is set to a value higher than the voltage level obtained by the power supply voltage V.sub.CC plus the threshold voltage V.sub.th of transistors Q21 to Q28. This is because of the following reason. When the device is operated with unstable power supply voltage V.sub.CC, the bit line potential sometimes becomes higher than the potential of the shared sense amplifier control signal. As a result, transistors Q21 to Q28 are rendered non-conductive, and there is a possibility that a read signal of the memory cell might not be transmitted to the input node of the sense amplifier.
As described above, by using a signal at the boosted voltage V.sub.PP level as the selected state of the shared sense amplifier control signal, it is possible to sufficiently transmit to a bit line pair a signal at the power supply voltage V.sub.CC level amplified by sense amplifier 21 or 22, making it possible to enhance reliability of the device.
A detailed description will be given of the BLI driver with reference to the drawings. FIG. 11 is a circuit diagram showing the configuration of BLI driver 281.
BLI driver 281 includes a level converting unit 285, and a level selecting unit 286. Level converting unit 285 includes transistors Q281 to Q284. Level selecting unit 286 includes transistors Q285, Q286. It should be noted that transistors Q281, Q283, Q285 are p-channel MOS transistors, and that transistors Q282, Q284, Q286 are n-channel MOS transistors.
Transistor Q281 is connected to the boosted voltage V.sub.PP and transistor Q282, with its gate connected to a connection portion of transistor Q283 and transistor Q284. Transistor Q282 is connected to the ground potential GND, and supplied with the control signal BLIK0 at its gate. Transistor Q283 is connected to the boosted voltage V.sub.PP, with its gate connected to a connection portion of transistor Q281 and transistor Q282. Transistor Q284 is connected to the ground potential GND, and supplied with the control signal BLIS0 at its gate.
Description will now be given of operation of level converting unit 285. When the control signal BLIS0 is at an "H" (the power supply voltage V.sub.CC) level, and the control signal BLIK0 is at an "L" (the ground potential GND) level, transistors Q281 and Q284 are turned on, and transistors Q282 and Q283 are turned off. As a result, a node 287 attains an "L" (the ground potential GND) level. When the control signal BLIS0 is at an "L" level, and the control signal BLIK0 is at an "H" (the power supply voltage V.sub.CC) level, transistors Q281 and Q284 are turned off, and transistors Q282 and Q283 are turned on. As a result, node 287 attains an "H" (the boosted voltage V.sub.PP) level. Therefore, if the control signal BLIK0 is input at the power supply voltage V.sub.CC level, node 287 attains the boosted voltage V.sub.PP level, making it possible to convert a signal at the power supply voltage V.sub.CC level into a signal at the boosted voltage V.sub.PP level.
Level selecting unit 286 includes transistors Q285, Q286. Transistor Q285 is connected to the boosted voltage V.sub.PP and transistor Q286, with its gate connected to node 287. Transistor Q286 is connected to the ground potential GND, and supplied with the control signal BLIK0 at its gate.
Description will now be given of operation of level converting unit 286. When the control signal BLIK0 is at an "L" level, and node 287 is at an "L" level, transistor Q285 is turned on, and transistor Q286 is turned off. As a result, a signal at an "H" (the boosted voltage V.sub.PP) level is output as the shared sense amplifier control signal BLI0. When the control signal is at an "H" (the power supply voltage V.sub.PP) level, and node 287 is at an "H" (the boosted voltage V.sub.PP) level, transistor Q285 is turned off, and transistor Q286 is turned on. As a result, a signal at an "L" level is output as the shared sense amplifier control signal BLI0.
Because of the above-described operation, it is possible to convert the control signal BLIS0 signal at the power supply voltage V.sub.CC level into the shared sense amplifier control signal BLI0 at the boosted voltage V.sub.PP level. Although the above description is given with respect to BLI driver 281, BLI drivers 282 to 284 have the same configuration. BLI drivers 282 to 284 can implement the same operation.
Description will now be given of signal waveforms of the control signals BLIS0, BLIK0 and the shared sense amplifier control signal BLI0. FIG. 12 is a diagram showing signal waveforms of the control signals BLIS0, BLIK0, and the shared sense amplifier control signal BLI0. As shown in FIG. 12, the control signal BLIS0 and the control signal BLIK0 are complementary to each other. At the time of stand-by of the device, the control signal BLIS0 is at an "H" (the power supply voltage V.sub.CC) level, and the control signal BLIK0 is at an "L" level. At this time, the shared sense amplifier control signal BLI0 output from BLI driver 281 is at an "H" (the boosted voltage V.sub.PP) level. When the device enters an active state, the control signal BLIS0 falls, and the control signal BLIK0 rises. At this time, the shared sense amplifier control signal BLI0 falls and attains an "L" level, that is, a state where the sense amplifiers are not selected. When the device completes the active state and enters again the stand-by state, the control signal BLIS0 rises, and the control signal BLIK0 falls. At this time, the shared sense amplifier control signal BLI0 rises to an "H" (the boosted voltage V.sub.PP) level, and the device enters the stand-by state.
In order to ensure stability of the operation, a boosted voltage higher than the power supply voltage is used as described above. In this case, when the voltage is converted from the power supply voltage to the boosted voltage, a loss is caused by boosting. When it is intended to obtain an abrupt rise of the voltage up to the boosted voltage V.sub.PP level, a larger current is to be consumed. Therefore, as described above, when the device changes its state from the active state to the stand-by state, if it is intended to obtain an abrupt rise of the shared sense amplifier control signal from the ground potential level to the boosted voltage level, it is necessary to make a larger current flow in order to compensate for a loss caused by boosting, which increases power consumption.
In such a dynamic type semiconductor memory device as described above, a signal line transmitting a shared sense amplifier control signal becomes long, and a load capacitance of the signal line becomes large. Therefore, increase in current consumption caused by the above-described boosting becomes very large, and power consumption of the entire device is substantially increased.